| 摘要 |
<p>An improved fractional divider that provides high resolution without the need for any analog components. It comprises an integer value storage means containing the integer part of the division value 'K' connected to the input of a programmable counter means that is configured for a count value of 'K' or 'K+1' depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces said count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.
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