发明名称 |
SEMICONDUCTOR MEMORY DEVICE HAVING CHARGE-TRAPPING MEMORY CELLS |
摘要 |
The memory cell is arranged in a ridge (15) of semiconductor material forming a fin (1) with sidewalls and a channel region between source and drain regions (2). Memory layer sequences (4), such as ONO, provided for charge-trapping are applied to the sidewalls, and gate electrodes are arranged on both sides of the ridge. A plurality of ridges at a distance parallel to one another and have sidewalls facing a neighboring ridge form an array of charge-trapping memory cells. Wordlines are arranged between the ridges, sections of the wordlines forming the gate electrodes (3). This arrangement enables a double gate operation of the cells and thus allows for a storage of four bits of information in every single memory cell structure. |
申请公布号 |
WO2006034854(A3) |
申请公布日期 |
2006.06.22 |
申请号 |
WO2005EP10470 |
申请日期 |
2005.09.28 |
申请人 |
INFINEON TECHNOLOGIES AG;VERHOEVEN, MARTIN |
发明人 |
VERHOEVEN, MARTIN |
分类号 |
H01L27/115;G11C16/04;H01L21/336;H01L21/768;H01L21/8247;H01L27/02;H01L29/786;H01L29/788;H01L29/792 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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