发明名称 |
Method of manufacturing a SiC vertical MOSFET |
摘要 |
A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO<SUB>2</SUB>.
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申请公布号 |
US2006134847(A1) |
申请公布日期 |
2006.06.22 |
申请号 |
US20060353992 |
申请日期 |
2006.02.15 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TARUI YOICHIRO;OHTSUKA KEN-ICHI;IMAIZUMI MASAYUKI;SUGIMOTO HIROSHI;TAKAMI TETSUYA |
分类号 |
H01L21/265;H01L21/8238;H01L21/04;H01L21/266;H01L21/336;H01L29/10;H01L29/12;H01L29/24;H01L29/78 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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