发明名称 Apparatus for selecting and outputting either a first clock signal or a second clock signal
摘要 By using a CR oscillating circuit and a PLL oscillating circuit selectively, these two oscillating circuits are used as a high frequency, low power consumption, short waiting time for stable oscillation, and low operating voltage oscillating circuit.
申请公布号 US7065668(B2) 申请公布日期 2006.06.20
申请号 US20040936986 申请日期 2004.09.09
申请人 SEIKO EPSON CORPORATION 发明人 KOSUDA TSUKASA;HAYAKAWA MOTOMU
分类号 G04G3/00;G06F1/04;G06F1/06;G06F1/08;G06F1/16;G06F3/03;G06F3/033 主分类号 G04G3/00
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