发明名称 Cascadable current-mode regulator
摘要 A cascadable power regulator including a programmable delay unit and PWM control logic. The programmable delay unit initiates a delay period in response to a digital input signal and asserts a digital output signal upon expiration of the delay period. The PWM control logic controls a PWM cycle in response to the digital input signal and in response to an output control condition. The cascadable regulator uses digital signals to communicate between channels. Digital signals are not prone to the same kind of signal degradation or noise susceptibility as analog signals. Thus, the number of phases is not limited, the physical separation between the regulators is not limited, and the switching frequency is not as limited. There is no clock signal from a separate controller so that the controller is a relatively simple, low-cost device. Since there is no clock, a unique self-oscillating system is achieved using the cascadable regulator.
申请公布号 US7061215(B2) 申请公布日期 2006.06.13
申请号 US20030739757 申请日期 2003.12.18
申请人 INTERSIL AMERICAS INC. 发明人 HARRIS MATTHEW B.
分类号 G05F1/40;H02J1/10;H02M3/158;H02M3/28 主分类号 G05F1/40
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