| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase comparison circuit capable of suppressing a phase comparison result from being greatly deviated even when a clock signal to be compared is not normal. SOLUTION: Even when a "0" level section for a short period exsists in a "1" level section of a comparison clock 102, a clock abnormity detection section 107 detects that a second rising edge is generated in the comparison clock 102 with respect to one rising edge of a reference clock 101 and provides an output of a clock abnormity signal 108. Since a phase comparison section 109 receives the clock abnormity signal 108, does not carry out phase comparison at the second rising edge of the comparison clock 102 and outputs a phase comparison result 110 equal to that when the comparison clock 102 is normal, even in the case of abnormity such that the "0" level section for a short period exsists in the "1" level interval of the comparison clock 102, it is suppressed that the phase comparison result is greatly deviated. COPYRIGHT: (C)2006,JPO&NCIPI
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