| 摘要 |
<p>A first insulating layer (15), a charge accumulation layer (17), and a second insulating layer (19) are formed in this order over a channel region interposed between a pair of diffusion layers (13A, 13B). On the second insulating layer (19), two control gate layers (21A, 21B) spaced with a gap (G1) in the intermediate part in the channel width direction are provided. Discrete charge traps are provided in the charge accumulation layer (17) to restrict the move of charges in the layer. The charges injected in accordance with a write voltage applied to the control gate layer (21A, 21B) can be localized in the charge accumulation layer (17) under the control gate layer (21A, 21B). Charge accumulation or charge non-accumulation of charge accumulation region under the control gate layers (21A, 21B) can be controlled, and multilevel storage in a memory cell is possible.</p> |
