| 摘要 |
PROBLEM TO BE SOLVED: To reduce cost by miniaturizing a chip size and improving defect rate with simple process. SOLUTION: Many pieces of chip elements 3 and wiring patterns 7 are formed on a wafer 30, and the wafer is diced after a cap substrate 4 is mounted opposed to each chip element through a junction seal layer 5 having a predetermined thickness. A chip element storage space part 6 sealing the chip element 3 is constituted between a main surface 2a of the chip substrate 2 and a first main surface 4a of the cap substrate 4. COPYRIGHT: (C)2006,JPO&NCIPI
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