发明名称 |
INTEGRATED CIRCUIT SELF-TEST ARCHITECTURE |
摘要 |
<p>An integrated circuit (1) comprises a monitor (Ml, M3, M3) operable to produce monitor data in dependence upon a measured parameter of the integrated circuit (1); and a self test controller (28) connected to receive monitor data from the monitor (Ml, M2, M3). The self-test controller is also operable to output self test data from the integrated circuit. The monitor includes an output shift register (SRl, SR2, SR3) and is operable to output monitor data through the shift register (SRl, SR2, SR3). Such a system enables simplified communication of system self test results on an integrated circuit.</p> |
申请公布号 |
WO2006056951(A1) |
申请公布日期 |
2006.06.01 |
申请号 |
WO2005IB53883 |
申请日期 |
2005.11.23 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;PELGROM, MARCEL;VEENDRICK, HENDRICUS, J., M. |
发明人 |
PELGROM, MARCEL;VEENDRICK, HENDRICUS, J., M. |
分类号 |
G01R31/3185;G01R31/3167 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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