发明名称 |
SCALABLE INTEGRATED LOGIC AND NON-VOLATILE MEMORY |
摘要 |
<p>A scalable, logic transistor has a pair of doped regions for the drain and source. A gate insulator layer is formed over the substrate and between the drain and source regions. A gate stack is formed of a gate layer, such as polysilicon or metal, between two metal nitride layers. A compatible non-volatile memory transistor can be formed from this basic structure by adding a high-K dielectric constant film with an embedded metal nano-dot layer between the tunnel insulator and the gate stack.</p> |
申请公布号 |
WO2006057773(A1) |
申请公布日期 |
2006.06.01 |
申请号 |
WO2005US39391 |
申请日期 |
2005.11.01 |
申请人 |
MICRON TECHNOLOGY, INC.;BHATTACHARYYA, ARUP |
发明人 |
BHATTACHARYYA, ARUP |
分类号 |
H01L29/423;H01L21/28;H01L21/336 |
主分类号 |
H01L29/423 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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