| 摘要 |
A method and system are disclosed for balancing a plurality of flip-flops across a number of global scan chains in a design of a digital integrated circuit chip. The design of the chip is organized into a number of discrete blocks such that each of the discrete blocks comprises a plurality of flip-flops. Within each discrete block, the plurality of flip-flops is connected to form a number of sub-chains of flip-flops. The sub-chains are then connected, within and across the discrete blocks, to generate a number of global scan chains such that the resultant number of flip-flops in each global scan chain is substantially the same.
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