Schwebende Bitleitungen Prüfmodus mit digital steuerbaren Bitleitungen-Abgleichschaltungen

摘要

The method involves generating a dummy timing cycle for disabling bitline equalizer by supplying a negative test pulse. The bitline equaliser is disabled to set up a floating bitline test mode. A row address strobe signal is enabled and read operation is started in a normal mode. Defective bitlines are detected during dummy timing cycles.