发明名称 GRADATION VOLTAGE GENERATION CIRCUIT AND GRADATION VOLTAGE GENERATION METHOD
摘要 PROBLEM TO BE SOLVED: To reduce a chip area required for an operational amplifier provided in a gradation voltage generation circuit. SOLUTION: The gradation voltage generation circuit 10 relating to this invention comprises: a ladder resistor 11 provided with a plurality of resistors R0-Rn serially connected between a high potential reference voltage VDD and a low potential reference voltage VSS; a selector circuit 12 for selecting one voltage from the voltages between the resistors provided in the ladder resistor 11; an input stage/drive stage circuit 13 for turning the voltage selected by the selector circuit 12 to an input voltage; a plurality of output stage circuits 14 and 15 driven by the input stage/drive stage circuit 13 for outputting a gradation voltage; capacitors CP1, CN1, CP2 and CN2 for holding a driving voltage applied from the input stage/drive stage circuit 13 to the output stage circuits 14 and 15; and a switch for switching the connecting destination of the input stage/drive stage circuit 13 between the plurality of output stage circuits 14 and 15. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006078731(A) 申请公布日期 2006.03.23
申请号 JP20040262113 申请日期 2004.09.09
申请人 NEC ELECTRONICS CORP 发明人 MIURA MAKOTO
分类号 G09G3/36;G02F1/133;G09G3/20 主分类号 G09G3/36
代理机构 代理人
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