| 摘要 |
<p>An output buffer (500) is disclosed that includes an output driver circuit (508) having a first drive transistor (P504) for driving an output node (520) to a first logic level according the potential at a first pre-drive node (516), and a second drive transistor (N504) for driving the output node (520) to a second logic level according the potential at a second pre-drive node (518). The potential at the first pre-drive node (516) is established by a first standard pre-drive circuit (504) and a first phased pre-drive circuit (512). The potential at the second pre-drive node (518) is established by a second standard pre-drive circuit (506) and a second phased pre-drive circuit (514). In a low voltage mode of operation, where the rate of current drawn (di/dt) by the output driver circuit (508) is reduced, the standard and phased pre-drive circuits (504, 506, 512, 514) function together to drive their respective pre-drive nodes. In a high voltage mode of operation, where output driver circuit (508) di/dt is increased, the phased pre-drive circuits (512 and 514) are enabled a predetermined delay after the standard pre-drive circuits (504 and 506). <IMAGE></p> |
