发明名称 |
Methodology to optimize hierarchical clock skew by clock delay compensation |
摘要 |
A method for synthesizing a clock distribution system within an integrated circuit for compensating for clock skew within a global or top level clock distribution network begins with allocating at least one delaying circuit within each of functional circuits of the integrated circuit. An intra-functional clock distribution network is fabricated within each of the functional circuits. Once the intra-functional clock distribution network is fabricated, an inter-functional clock distribution network is constructed between each of the functional circuits. A clock skew for the inter-functional clock distribution network is determined. The clock skew is then compensated by inserting the delaying circuit at a terminal of the inter-function clock distribution network where each of the functional circuits is connected to the inter-functional clock distribution network.
|
申请公布号 |
US7017132(B2) |
申请公布日期 |
2006.03.21 |
申请号 |
US20030706380 |
申请日期 |
2003.11.12 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
HOU CLIFF;CHENG CHIA-LIN;LU LEE-CHUNG |
分类号 |
G06F17/50;G06F1/10;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|