发明名称 MEMORY CIRCUIT FOR ARITHMETIC PROCESSING UNIT
摘要 PROBLEM TO BE SOLVED: To provide a memory circuit for an arithmetic processing unit capable of physically reducing a capacity of a command storage memory. SOLUTION: The arithmetic processing unit is provided with an input memory 2 storing a plurality of input data, one or more computing units 1 for carrying out logic operation and numeric comparison or the like, an output memory 3 storing an arithmetic result from the computing unit 1, one or more command storage memories 4 for determining a process to be executed by the computing unit 1, and a program counter 9 counting up every execution cycle of the computing unit 1. It is provided with a register 7 storing a particular command code frequently used in arithmetic processing, a particular command information storage memory 6 for storing information of a step executing the particular command stored in the registered 7, an address generating counter 5 capable of controlling count operation by using output data from the particular command information storage memory 6 as a counting prohibition signal, and a selector circuit 8 carrying out switching between an output command from the command storage memory 4 and an output command from the register 7 storing the particular command code. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006072961(A) 申请公布日期 2006.03.16
申请号 JP20050064818 申请日期 2005.03.09
申请人 YASKAWA ELECTRIC CORP 发明人 SODA RYUICHI
分类号 G06F9/30;G06F9/38 主分类号 G06F9/30
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