发明名称 IMAGE OUTPUT APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide an image output apparatus realizing exact output processing using a low rate clock. SOLUTION: Image data belonging to a zoom area assigned to an SDRAM 26 is outputted in raster scan mode. A memory control circuit 24 transfers image data of 144 pixels continuous from a specified pixel in the horizontal direction from the SDRAM 26 to an image buffer 30. Image data stored in the image buffer 30 undergoes zoom processing in a zoom circuit 32. A buffer control circuit 28 judges whether the image data of 144 pixels continuous from a specified pixel in the horizontal direction includes the pixel data at the end of the zoom area in the horizontal direction. Furthermore, the buffer control circuit 28 updates the specified pixel in a mode dependent on the judgment results every time when transfer of the image data of 144 pixels is completed. COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2006050132(A) 申请公布日期 2006.02.16
申请号 JP20040226610 申请日期 2004.08.03
申请人 SANYO ELECTRIC CO LTD 发明人 MATSUMURA HIDEKI
分类号 H04N5/232;H04N5/228;H04N101/00 主分类号 H04N5/232
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