发明名称 |
Method and apparatus for a TFT array |
摘要 |
A testing method for a TFT array substrate arranging pixels in a matrix where a pixel comprises a pixel selection transistor having a gate formed from a first structural material and a source and a drain formed from a second structural material, and a drive transistor having a gate formed from the first structural material and a source and a drain formed from the second structural material, wherein the testing method comprises: a first step for applying a first voltage to the drain of the pixel selection transistor and initializing the source voltage; a second step for applying a second voltage to the drain of the pixel selection transistor and measuring the current flowing between the drain and source of the pixel selection transistor; and a third step for determining the on-state resistance of the pixel selection transistor from the current and the potential difference between the first voltage and the second voltage.
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申请公布号 |
US2006033447(A1) |
申请公布日期 |
2006.02.16 |
申请号 |
US20050173789 |
申请日期 |
2005.07.01 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
CHIKAMATSU KIYOSHI;TAJIMA KAYOKO |
分类号 |
G09G3/10 |
主分类号 |
G09G3/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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