| 摘要 |
A Phase Locked Loop ( 1 ) comprising a frequency detector ( 10 ) including a balanced quadricorrelator ( 2 ), the loop ( 1 ) being characterized in that the quadricorrelator ( 2 ) comprises double edge clocked bi-stable circuits ( 21, 22, 23, 24, 25, 26, 27, 28 ) coupled to multiplexers ( 31, 32, 33, 34 ) being controlled by a signal having the same bitrate as the incoming D signal (D).
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