| 摘要 |
A control circuit of a read operation of a semiconductor memory device is provided to secure an operation margin by varying a data output time interval. A first delay part(315) receives a sensing enable signal, generates a first delay signal, and outputs the first delay signal to a first global input/output line driver. The first delay part generates a second delay signal, and outputs the second delay signal to a second global input/output line driver. A second delay part(317) generates a pipe latch control signal according to the first delay signal and the second delay signal. A signal separation part(319) outputs a first pipe latch control signal and a second pipe latch control signal from the pipe latch control signal. The first delay part includes a first delay device, a latch, and a second delay device.
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