ARRAY SUBSTRATE, DISPLAY PANEL AND METHOD FOR PREPARING ARRAY SUBSTRATE

摘要

The invention provides an array substrate, a display panel and a method for preparing an array substrate. The array substrate includes multiple low temperature poly-silicon (LTPS) thin film transistors arranged in an array. Each LTPS thin film transistor includes: a substrate; a LTPS layer, a source, a drain and a first conductive layer disposed on a same surface of the substrate, the source and the drain respectively being arranged at two sides of the LTPS layer and electrically connected with the LTPS layer, the drain being electrically connected with the first conductive layer; an insulating layer disposed on the LTPS layer, the source, the drain and the first conductive layer; a gate disposed on the insulating layer and corresponding to the LTPS layer; a passivation layer disposed on the gate; and a second conductive layer disposed on the passivation layer and corresponding to the first conductive layer.

主权项

1. An array substrate comprising a plurality of low temperature poly-silicon thin film transistors arranged in an array, each of the plurality of low temperature poly-silicon thin film transistors comprising:
a substrate; a low temperature poly-silicon layer, a source, a drain and a first conductive layer disposed on a same surface of the substrate, wherein the low temperature poly-silicon layer is disposed at a middle portion of the surface of the substrate, the source and the drain respectively are disposed at two sides of the low temperature poly-silicon layer, an end of the source is electrically connected to an end of the low temperature poly-silicon layer, an end of the drain is electrically connected to another end of the low temperature poly-silicon layer, and another end of the drain is electrically connected to the first conductive layer; an insulating layer disposed on the low temperature poly-silicon layer, the source, the drain and the first conductive layer; a gate disposed on the insulating layer and corresponding to the low temperature poly-silicon layer; a passivation layer stacked on the gate; and a second conductive layer disposed on the passivation layer and corresponding to the first conductive layer, wherein the first conductive layer is used as a pixel electrode, and the second conductive layer is used as a common electrode.