发明名称 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit
摘要 A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
申请公布号 US6996736(B1) 申请公布日期 2006.02.07
申请号 US20020076172 申请日期 2002.02.12
申请人 ALTERA CORPORATION 发明人 NGUYEN TRIET;JEFFERSON DAVID;REDDY SRINIVAS;STREICHER KEONE
分类号 G06F1/10 主分类号 G06F1/10
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