| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a clock supply circuit for suppressing the occurrence of clock skew by reducing deterioration over time due to the NBTI that is a problem of the reliability of MOS transistors used at conduction of a clock signal CLK, when the clock signal CLK is stopped. <P>SOLUTION: The clock supply circuit for supplying or stopping a clock signal CLK to / from flip-flops 42a, 42b on the basis of a received enable signal EN is configured to include a buffer 1 for propagating the received clock signal; multiple-input gates 22, 32a, 32b, 32a', 32b' which are arranged between the buffer 1 and the flip-flops 42a, 42b, receive the clock signal CLK and the enable signal EN propagated from the buffer 1, and carry out gate operation of the operation and stop of the clock signal CLK, depending on the combination of respective logical values of the received clock signal CLK and enable signal EN, and the PMOS transistor 324 of the final stage in the multiple-input gates 22, 32a, 32b, 32a', 32b' connected to the flip-flops 42a, 42b is brought into an OFF-state at operation stop of the clock signal CLK. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
