发明名称 |
Semiconductor memory devices and method of sensing bit line thereof |
摘要 |
A semiconductor memory device and a bit line sensing method thereof are disclosed. The semiconductor memory device includes a first memory cell connected between a first word line accessed by a first address and an inverted bit line; a second memory cell connected between a second word line accessed by a second address and a bit line; a first type sense amplifier serially connected between the bit line and the inverted bit line and having a first type first MOS transistor sensing the inverted bit line and a first type second MOS transistor sensing the bit line if a first enable signal of a first voltage is applied; a second type first sense amplifier serially connected between the bit line and the inverted bit line and having a second type first MOS transistor sensing the inverted bit line and a second type second MOS transistor sensing the bit line if a second enable signal of a second voltage is applied, wherein the second type first MOS transistor has a better sensing ability than the second type second MOS transistor; and a second type second sense amplifier serially connected between the bit line and the inverted bit line and having a second type third MOS transistor sensing the inverted bit line and a second type fourth MOS transistor sensing the bit line if a third enable signal of the second voltage is applied, wherein the second type fourth MOS transistor has a better sensing ability than the second type third MOS transistor.
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申请公布号 |
US2006023537(A1) |
申请公布日期 |
2006.02.02 |
申请号 |
US20050185351 |
申请日期 |
2005.07.20 |
申请人 |
LEE HYUN-SEOK;CHOI JONG-HYUN;CHUN KI-CHUL;LEE JONG-EON |
发明人 |
LEE HYUN-SEOK;CHOI JONG-HYUN;CHUN KI-CHUL;LEE JONG-EON |
分类号 |
G11C7/02 |
主分类号 |
G11C7/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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