| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of attaining IP fragmentation with a small storage capability. <P>SOLUTION: An IP reception processing circuit 30 includes an IP reception processing section 31; a fragment managing section 32; a fragmentation information recording section 33; a first reception queue 34; a high-order layer transfer processing section 35; and a second reception queue 36. When an IP datagram received from a lower-order layer by the IP reception processing section 31 is an IP fragment, the fragment managing section 32 generates or updates fragmentation information, compares an offset in the IP fragment with an offset in the fragmentation information, writes the IP fragment to the first reception queue 34 when they do not coincident with each other, or outputs the IP fragment to the high-order layer transfer processing section 35 when they do coincide, and updates the offset in the fragmentation information. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
