| 摘要 |
<p>A Sigma-Delta modulator(10) comprises a signal put(34) coupled to a forward filter comprising a series connection of a plurality of N summing stages(28, 30, 32), where N is an integer of at least 2, alternating with a corresponding plurality of integrating stages(40, 42, 44) and an analogue to digital converter(ADC)(18) having an input coupled to an output of the Nth integrating stage(44) and an output. A feedback filter comprises a feedback coupling from the output of the ADC(18) to a digital to analogue converter(DAC)(26) which is coupled to an input of each of the summing stages by way of respective weights(46, 48, 50). Control means(66) including switching means (58, 64) are provided for changing the order of the modulator. To reduce the order and increase the bandwidth, the control means by-passes the first(40) of the integrating stages and uses the second(42) of the integrating stages as a first of the integrating stages and vice versa to increase the order and decrease the bandwidth.</p> |
