| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which a test of its interface part can be performed especially for a memory LSI. SOLUTION: The device is provided with an expected value generating circuit 13a receiving an output signal for an internal memory circuit 11 from an I/F Ðart 12 and generating an expected value signal for detecting an error of the output signal, a comparing and determination circuit 13b comparing the output signal with the expected value signal and determining coincidence or noncoincidence, and an output processing circuit 13c holding the determination result of the comparison and the determination circuit 13b and performing processing when this determined result is outputted to the outside, when a test pattern being a pseudo random number signal of a M group is inputted to the I/F part 12 from a pulse generator 14 and a test is performed, a circuit based on a generation logic of the pseudo random number signal of the M group is provided in the expected value generating circuit 13a. COPYRIGHT: (C)2006,JPO&NCIPI
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