| 摘要 |
<p>Embodiments of this invention relate to implementing bussed transactions between component(s) connected to a system bus. A clock generator circuit generates an independent clock signal for each component connected to the system bus. The clock generator circuit may use system signals, sideband busses, component signals, controller signals, arbiter signals or other means to determine the target and/or initiator component(s) for a particular transaction. The individual clock signals may be gated or otherwise suppressed to selectively activate the components to participate in the transaction. If the components participating in a transaction are capable of operating at frequencies higher than the nominal system frequency, then the clock generator circuit may increase the frequency of the individual clock signals of the participating components during the course of the transaction. In particular embodiments, the system comprises one or more Cardbus or PCI slots for receiving Cardbus or PCI-compliant components.</p> |
