发明名称 STATUS BITS FOR CACHE MEMORY
摘要 DATA PROCESSING APPARATUSES PROVIDED COMPRISING A MEMORY (14) OPERABLE TO STORE A PLURALITY OF DATA WORDS, EACH DATA WORD BEING ASSOCIATED WITH AT LEAST ONE STATUS BIT (18) GIVING INFORMATION REGARDING A STATUS OF SAID DATA WORD; A STATUS BIT STORE (26) OPERABLE TO STORE SAID STATUS BITS WITHIN A HIERARCHICAL RELATIONSHIP SUCH THAT A COMBINED STATUS RELATING TO A PLURALITY OF FIRST LEVEL STATUS BITS (18) AT A FIRST LEVEL WITHIN SAID HIERARCHICAL RELATIONSHIP IS INDICATED BY A SECOND LEVEL STATUS BIT (22) AT A SECOND LEVEL WITHIN SAID HIERARCHICAL RELATIONSHIP, SAID SECOND LEVEL BEING HIGHER IN SAID HIERARCHICAL RELATIONSHIP THAN SAID FIRST LEVEL; AND STATUS QUERYING LOGIC (30) OPERATIVE TO DETERMINE A STATUS OF A DATA WORD WITHIN SAID MEMORY BY EXAMINING STATUS BITS WITHIN SAID STATUS BIT STORE STARTING AT A TOP LEVEL WITHIN SAID HIERARCHICAL RELATIONSHIP AND WORKING DOWN THROUGH SAID HIERARCHICAL RELATIONSHIP UNTIL A STATUS BIT IS REACHED THAT INDICATES SAID STATUS OF SAID DATA WORD INDEPENDENTLY OF ANY STATUS BITS LOWER IN SAID HIERARCHICAL RELATIONSHIP. IN THIS WAY A GLOBAL OR LARGESCALE CHANGE TO STATUS BITS MAY BE MADE BY MODIFYING RELATIVELY FEW HIGHER LEVEL STATUS BITS WITHIN THE HIERARCHICAL RELATIONSHIP THEREBY ACHIEVING A HIGH SPEED CHANGE WITH REDUCED LEVELS OF SPECIAL PURPOSE HARDWARE BEING REQUIRED. (FIGURE 2)
申请公布号 MY120377(A) 申请公布日期 2005.10.31
申请号 MYPI20000476 申请日期 2000.02.11
申请人 ARM LIMITED 发明人 SIMON CHARLES WATT
分类号 G11C15/00;G06F12/08;G06F15/00 主分类号 G11C15/00
代理机构 代理人
主权项
地址