| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a memory controller and a semiconductor device, allowing improvement of use efficiency of a data bus while suppressing increase of the number of terminals of the semiconductor device. <P>SOLUTION: This memory controller 121 is connected to an SRAM 122 allowing access by only a row address, a NOR type flash memory 123, and an SDRAM 124 allowing access by designating a row address and a column address. The data bus 107 is shared in time-sharing, and the other control lines are individually connected to the SRAM 122, the NOR type flash memory 123 and the SDRAM 124. An access request to each the memory device that is access destination is stored in a FIFO memory 201, and an SDRAM access section decision device 204 detects a data bus idle section wherein the SDRAM 124 does not permit the access. When the access request to the following SRAM 122 can be executed in the access non-permission section, order of the access requests of the FIFO memory 201 is exchanged such that the access request to the SRAM 122 becomes the head. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
