发明名称 DSRC COMMUNICATION CIRCUIT AND COMMUNICATION METHOD
摘要 <P>PROBLEM TO BE SOLVED: To flexibly adjust data transmission timing if slot timing deviates from frame timing by preventing the occurrence of a unique word detection error, even if timing of a unique word detecting window deviates from timing of reception data when the data reception frame switches. <P>SOLUTION: A bit counter 111 generates frame timing by a frame synchronization signal. A bit counter 112 generates slot timing upon receiving the frame synchronization signal. The unique word detecting window is generated from the frame timing, and reception arithmetic operation timing and data reception timing are generated from the slot timing. Also, the data transmission timing and transmission data arithmetic operation timing are generated on the basis of any one of the frame timing and the slot timing which are selected by a selector 123. <P>COPYRIGHT: (C)2006,JPO&NCIPI
申请公布号 JP2005303385(A) 申请公布日期 2005.10.27
申请号 JP20040112495 申请日期 2004.04.06
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 OYAMA SHIGEKI
分类号 H04J3/00;H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/00
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