| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid a situation where the layout area of a clamp circuit provided in the circuit of a semiconductor element and determining the DC level at a capacity coupled signal terminal is increased by a high resistance resistive element formed of polysilicon being employed therein. <P>SOLUTION: A comparator 22 compares a sine wave signal being inputted from a signal source 20 capacity coupled through a capacitor 24 to Vac terminal with a DC reference signal being inputted to Vdc terminal thus generating a clock signal. In order to clamp the DC level at the Vac terminal to the DC level at the Vdc terminal, the Vac terminal and the Vdc terminal are connected through the channels of MOSFETs 32 and 34. The MOSFETs 32 and 34 are set with gate voltages such that they operate under subthreshold characteristics. By the subthreshold characteristics, the MOSFETs 32 and 34 function as high resistances and transmit only DC level from the Vdc terminal side to the Vac terminal. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
