发明名称
摘要 A computer system for executing at high speed programs described in a machine language based on the stack architecture, comprising a data cache, a data buffer, a consolidated register file each entry of which is designed to hold data, an advanced pointer stack and a completed pointer stack each entry of which is designed to hold an entry address in the consolidated register file, an instruction buffer having the construction of a FIFO queue each entry of which is designed to hold substance of an instruction, and functional units including an arithmetic/logic unit and a load/store unit that can access the data cache and the data buffer. Each time an instruction is decoded, the advanced pointer stack and the consolidated register file are manipulated in accordance with the instruction, and substance of the instruction is written into the instruction buffer, and if necessary, into a free reservation station of an appropriate functional unit. Unexecuted instructions held in the instruction buffer are to be executed out of order. When the instruction held in the head entry of the instruction buffer is/becomes ready to be completed, in accordance with the substance in the head entry of the instruction buffer, the completed pointer stack is manipulated so as to reproduce the operation that was applied on the advanced pointer stack in the course of decoding of the held instruction, and the head entry is dequeued. <IMAGE>
申请公布号 JP3701203(B2) 申请公布日期 2005.09.28
申请号 JP20000614114 申请日期 2000.04.17
申请人 发明人
分类号 G06F9/30;G06F9/38;(IPC1-7):G06F9/38;G06F9/44 主分类号 G06F9/30
代理机构 代理人
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