发明名称 Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit
摘要 The invention relates to an automated method for inserting dummy surfaces ( 95 ) into the various layers of the physical design ( 121 ) of multilayer integrated circuits organized in interconnected units ( 2 ) containing interconnected blocks ( 30 ) composed of interconnected cells ( 3 ), implemented by an integrated circuit design system ( 100 ). The multilayer integrated circuit design ( 121 ), stored in the design system ( 100 ) is implemented layer by layer, through selective insertion of patterns of dummy surfaces ( 95 ), the selective insertion is based on an insertion hierarchy that respects the hierarchy of the physical design ( 121 ) of the integrated circuits, by means of individual implementation of the interconnected blocks ( 30 ) and first interconnection routing ( 31 ) for said interconnected blocks ( 30 ) and individual implementation of the interconnected units ( 2 ) and second interconnection routing ( 22 ) for said interconnected units ( 2 ). The patterns of dummy surfaces are established selectively in accordance with the design of the blocks ( 30 ) of the integrated circuit.
申请公布号 US2005210435(A1) 申请公布日期 2005.09.22
申请号 US20050065280 申请日期 2005.02.25
申请人 ZORRILLA MARTA;BLANCHARD VIVIAN 发明人 ZORRILLA MARTA;BLANCHARD VIVIAN
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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