发明名称 Memory module having an integrated circuit buffer device
摘要 A memory module includes an integrated circuit buffer device that receives control information via a connector interface. A first plurality of signal lines carries a first address from the integrated circuit buffer device to a first memory device. A second plurality of signal lines carries a first control signal from the integrated circuit buffer device to the first memory device. The first control signal specifies a read operation by the first memory device such that the first memory device provides first data, accessed from a memory location in the first memory device based on the first address, to the integrated circuit buffer device. A first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control signal from the integrated circuit buffer device to the first memory device. A third plurality of signal lines carries a second address from the integrated circuit device to the second memory device. A fourth plurality of signal lines carries a second control signal from the integrated circuit buffer device to the second memory device. The second control signal specifies a read operation. The second control signal corresponds to the control information. A second signal line carries a second signal from the integrated circuit buffer device to the second memory device. The second signal synchronizes communication of the second control signal from the integrated circuit buffer device to the second memory device. A transmitter circuit is disposed on the integrated circuit buffer device.
申请公布号 US2005210196(A1) 申请公布日期 2005.09.22
申请号 US20050128904 申请日期 2005.05.13
申请人 PEREGO RICHARD E;SIDIROPOULOS STEFANOS;TSERN ELY 发明人 PEREGO RICHARD E.;SIDIROPOULOS STEFANOS;TSERN ELY
分类号 G06F12/00;G06F13/16;G11C5/00;G11C7/10;G11C29/02;(IPC1-7):G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址