| 摘要 |
PROBLEM TO BE SOLVED: To define setup time and hold time of input data in relation to the input clock and I/O path delay time of output data in relation to the input clock when the clock of a built-in PLL is used in a macro cell. SOLUTION: Output terminals A6, A7 of the internal clock generated at the built-in PLL are provided, one clock output terminal A6 is directly connected to a clock input terminal A2 of a latch 12 for data input, and the other clock output terminal A7 is directly connected to a clock input terminal A4 of a latch 14 for data output. COPYRIGHT: (C)2005,JPO&NCIPI
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