发明名称 |
Semiconductor integrated circuit device |
摘要 |
A plurality of logic circuits both access the DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.
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申请公布号 |
US2005201193(A1) |
申请公布日期 |
2005.09.15 |
申请号 |
US20050074897 |
申请日期 |
2005.03.09 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KURODA NAOKI;NAKAI YUJI |
分类号 |
G06F12/00;G06F12/04;G11C7/00;G11C8/00;G11C11/4063;(IPC1-7):G11C8/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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