| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To enhance the reliability of system buildup by recognizing a reset type. <P>SOLUTION: A clock signal d transmitted from a crystal oscillator 11 is fed to a 2-stage sampling circuit 12, which samples a power-on reset signal a output from a power supply monitor IC 1 by using the clock signal d. A status latch signal f is produced in an output from the circuit 12 and this signal f is fed to a power-on reset status register 13. The power-on reset signal a and a power-on reset status clear signal e controllable by an internal register of an FPGA 5 are fed to an OR circuit 14. The data status register 13 is latched by the status latch signal f output from the sampling circuit 12 and the production of the power-on reset signal a at an output terminal of the power supply monitor IC 1 can be confirmed by the latching operation. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
