发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a PLL circuit for reducing EMI noise by a simple mechanism. <P>SOLUTION: The PLL circuit comprises an oscillation circuit for generating an oscillation signal having an oscillation frequency based on a supplied voltage, a frequency divider for generating a comparison signal by dividing the generated oscillation signal based on the number of a predetermined frequency divisions, a phase comparator for generating a phase difference signal between the generated comparison signal and a reference signal, a low-pass filter for generating a voltage signal by making the generated phase difference signal a DC signal and supplying it to the oscillation circuit, a control unit for switching at a predetermined timing about enable/disable for the phase difference signal supplied from the phase comparator to the low pass filter, and a resistor element arranged between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter. When the phase difference signal is made into enable, the oscillation circuit is oscillation-operated based on the voltage signal according to the phase difference signal. When the phase difference signal is made into disable, the predetermined potential is supplied to the low pass filter through the resistor element, and the oscillation circuit is oscillation-operated based on the voltage signal generated according to the supplied predetermined potential. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005244876(A) 申请公布日期 2005.09.08
申请号 JP20040055280 申请日期 2004.02.27
申请人 SANYO ELECTRIC CO LTD 发明人 KIMURA SHUJI;HASHIZUME TAKASHI
分类号 H03L7/18;G06F1/04;H03C3/00;H03L7/093 主分类号 H03L7/18
代理机构 代理人
主权项
地址