Clock restoration circuit using up/down signal generator with compensation of delay in a loop,申请号KR20030034926-传众专利搜索

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发明名称	Clock restoration circuit using up/down signal generator with compensation of delay in a loop
摘要
申请公布号	KR100511364(B1)	申请公布日期	2005.08.31
申请号	KR20030034926	申请日期	2003.05.30
申请人		发明人
分类号	H03K5/12;(IPC1-7):H03K5/12	主分类号	H03K5/12
代理机构		代理人
主权项
地址

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