发明名称 EARLY-LATE SYNCHRONIZER HAVING REDUCED TIMING JITTER
摘要 A device for maintaining fine alignment between an incoming spread spectrum signal and a locally generated code in a digital communication receiver comprises: - a delay line (56) for storing a plurality of consecutive samples (E-1, E, M, L, L+1) of the incoming spread spectrum signal; - three digitally controlled interpolators (24, 26, 28) for determining by interpolation between consecutive samples an interpolated early sample (e), an interpolated middle sample (m) and an interpolated late sample (1); - two correlators (30, 32) for calculating an error signal (Sigma) as the difference between the energy of the symbols computed from the interpolated early (e) and late (1) samples; - a circuit for generating a control signal (SOUT) for controlling the interpolation phase of the digitally controlled interpolator (24) for the early sample (e), and - a digital non-linear filter (68), for smoothing the control signal (SOUT) of the interpolator (24) for the early sample (e), enabling the update operation of the control signal only when the absolute value (|Sigma(n)|) of the error signal at a time instant n is smaller than the absolute value (|Sigma(n-1)|) of the same error signal at a time instant n-1.
申请公布号 KR20050086639(A) 申请公布日期 2005.08.30
申请号 KR20057008656 申请日期 2005.05.13
申请人 TELECOM ITALIA S.P.A. 发明人 ETTORRE DONATO;GRAZIANO MAURIZIO;MELIS BRUNO;FINOTELLO ANDREA;RUSCITTO ALFREDO
分类号 H04B1/7073;(IPC1-7):H04B1/69 主分类号 H04B1/7073
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