Control method for the reading in of a data signal to an electronic circuit input latch, especially to a DRAM circuit, whereby the delay between signal and clock flanks is set so that it is within a defined time window

摘要

Method for controlling the reading in of a data signal to an input (E) of an electric circuit in an input latch (2) under the control of a clock signal (CLK). The datum displayed by the data signal in the input latch is carried over with a clock signal. The cycle flank of the clock signal is temporally displaced dependent on the time delay between a signal flank of the input signal and the clock signal flank such that the time delay between the two lies within a defined time window. Input circuit for an electronic circuit with an input latch (2) for temporary storage of a data signal.