发明名称 |
Model stamping matrix check technique in circuit simulator |
摘要 |
The present invention includes a method for detecting model stamping errors during circuit simulation without the need for golden data. The method checks for model stamping errors by determining whether entries in model stamping matrices interrelate according to a plurality of preset rules before circuit equations are solved.
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申请公布号 |
US2005177807(A1) |
申请公布日期 |
2005.08.11 |
申请号 |
US20040773541 |
申请日期 |
2004.02.06 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
MA YUTAO;MCGAUGHY BRUCE W.;LIU ZHIHONG |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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