| 摘要 |
A muxed-decoder circuit including multiple complementary input dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a complementary P-logic AND dynamic circuit, a complementary N-logic AND dynamic circuit and a pass device. The complementary P-logic AND dynamic circuit has an output coupled to a corresponding output evaluation node, and evaluates bits of an encoded address value corresponding and bits of a digital select value having a logic state for selecting the encoded address. The complementary N-logic AND dynamic circuit has an output coupled to a corresponding preliminary evaluation node, and evaluates inverted bits of the address value and the digital select value. The pass device is coupled between corresponding first and second evaluation nodes and drives the second evaluation node low if the complementary N-logic AND dynamic circuit fails to evaluate. The AND logic gate couples to the output evaluation nodes and provides a corresponding decoded bit.
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