发明名称 |
Counter system and method |
摘要 |
A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding addends to the plurality of counts. A count engine controls the adding of the addends to the plurality of counts.
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申请公布号 |
US6922456(B2) |
申请公布日期 |
2005.07.26 |
申请号 |
US20020106536 |
申请日期 |
2002.03.25 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
GREENLAW JONATHAN E.;O'CONNOR PAUL |
分类号 |
G04F1/00;G04F3/00;G04F5/00;G04F7/00;G04F8/00;G04F10/00;G04G5/00;G04G7/00;G04G15/00;G06F15/00;G06M3/00;H03K21/02;(IPC1-7):G06M3/00 |
主分类号 |
G04F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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