| 摘要 |
PROBLEM TO BE SOLVED: To reduce idle time of a processor in a caching mistake, in relation to design and operation of a cache memory and support hardware for a processing unit of a digital data processing device. SOLUTION: A computer cache memory having at least two levels includes associativity sets allocated to congruence groups, each congruence group having multiple associativity sets (preferably two) in the higher level cache and multiple associativity sets (preferably three) in the lower level cache. The address range of an associativity set in the higher level cache is distributed among all the associativity sets in the lower level cache within the same congruence group, so that these lower level associativity sets are effectively shared by all associativity sets in the same congruence group in the higher level. The lower level cache is preferably a victim cache of the higher level cache. COPYRIGHT: (C)2005,JPO&NCIPI
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