发明名称 |
Predicting instruction branches with independent checking predictions |
摘要 |
Systems and methods of predicting instruction branches provide for independent checking predictions and dynamic next-line predictions. Next-line predictions may also have a latency that is a plurality of clock cycles, where the next line predictions include group predictions. Each group prediction includes a plurality of target addresses corresponding to their plurality of clock cycles. The plurality of target addresses can include a leaf target and one or more intermediate targets, where the leaf target defines a target address of the group prediction.
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申请公布号 |
US2005132174(A1) |
申请公布日期 |
2005.06.16 |
申请号 |
US20030735675 |
申请日期 |
2003.12.16 |
申请人 |
INTEL CORPORATION |
发明人 |
JOURDAN STEPHAN J.;PHELPS BOYD S.;DAVIS MARK C. |
分类号 |
G06F9/00;G06F9/38;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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