| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method for relaxing alignment accuracy conditions in the manufacturing of an integrated circuit. <P>SOLUTION: The method for relaxing the alignment accuracy conditions in the manufacturing of an integrated circuit includes steps of forming a mask layer 102 on a substrate and forming a plurality of first apertures 104 in the mask layer. Then the first apertures are filled with a buffer layer, and a photoresist layer is formed on the substrate and patterned to form second apertures which expose a part of the buffer layer. The substrate is subjected to isotropic etching to remove the buffer layer exposed through the second apertures and to expose the side walls of the first apertures. Further, the photoresist layer is removed to expose the mask layer having the aperture pattern and the embedded buffer layer. The mask layer is useful as a hard mask relating to the succeeding process. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
