发明名称 Packet processing device
摘要 A packet processing device in which a receiving buffer free space notifying portion notifies a free space of a receiving buffer, an accumulation condition determining portion determines a size of a big packet based on the free space, and a reassembly buffer processor reassembles a plurality of receiving packets into a single big packet to be transmitted to the receiving buffer. A backward packet inclusive information reading circuit for detecting the free space based on information within a backward packet from the upper layer may be used as the receiving buffer free space notifying portion. Also, an application layer may be used as the upper layer so that the big packet is transmitted not through a buffer of a transport layer but directly to the receiving buffer.
申请公布号 US6907042(B1) 申请公布日期 2005.06.14
申请号 US20000552135 申请日期 2000.04.19
申请人 FUJITSU LIMITED 发明人 OGUCHI NAOKI
分类号 H04L12/56;H04L29/08;(IPC1-7):H04L12/28 主分类号 H04L12/56
代理机构 代理人
主权项
地址