发明名称 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device inhibiting a short circuit among a gate electrode and source-drain sections and having a high melting-point metallic silicide layer reducing a leakage in a pn junction and having a high reliability. SOLUTION: A Co<SB>2</SB>Si silicide region 121 having a high resistance is formed to the upper sections of an n-type diffusion layer 108, a p-type diffusion layer 109, the n-type gate electrode 106, and the p-type gate electrode 105. Si ions 131 are implanted, and the whole is treated thermally for 5 to 90 sec within a temperature range from 600°C to 850°C. Accordingly, the leakage in the pn junction can be reduced because the consumption of substrate silicon atoms in a silicide reaction to CoSi<SB>2</SB>is inhibited and the abnormal growth of the metallic silicide layer can be suppressed. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005123301(A) 申请公布日期 2005.05.12
申请号 JP20030354850 申请日期 2003.10.15
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 MORITA KIYOYUKI;IMANAKA HIROBUMI;NIWAYAMA MASAHIKO;UMIMOTO HIROYUKI;AKAMATSU KAORI
分类号 H01L21/28;H01L21/265;H01L21/336;H01L21/8238;H01L27/092;H01L29/423;H01L29/49;H01L29/78;(IPC1-7):H01L21/28;H01L21/823 主分类号 H01L21/28
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